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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. october 2008 rev 1 1/24 24 SPDC12L00010 10 a dc/dc converter module features mtbf 1 000 000 (t a = 25 c) 10 a max output current input voltage range from 1.8 v to 14 v supply voltage range from 4.5 v to 14 v fixed or adjustable output voltage down to 0.6 v fixed frequency voltage mode control adjustable switching frequency soft-start and inhibit selectable uvlo threshold (5 v or 12 v bus) master/slave synchronization with 180 phase shift pre-bias star t-up capability selectable source/sink or source only capability after soft-start power good output with programmable delay over voltage protection with selectable latched/not-latched mode thermal shut-down operating temperature range -40 c 85 c applications laptop blade servers raid systems network routers cellular base stations industrial equipment test instrumentation medical diagnostic equipment points of load regulation table 1. device summary order code output voltage [v] input voltage [v] output ripple [mvpp] efficiency [%] notes SPDC12L00010 0.6 5 1.8 14 40 70 93 progr. output voltage www.st.com
contents SPDC12L00010 2/24 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin connection and mechanical data (dimensions in mm) . . . . . . . . . . . . . 5 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 thermal de-rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 auxiliary voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 multiple units synchroni zation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.6 power good signal and power good delay . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 oscillator setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.8 current sink-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.9 under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.10 program setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.11 voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.12 output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.13 additional loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.14 output over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.15 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.16 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.17 signal ground and power ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.18 input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPDC12L00010 contents 3/24 5.19 output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.20 phase connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 pcb footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
description SPDC12L00010 4/24 1 description the st SPDC12L00010 high density 10 a dc-dc converter is a complete step-down power supply. a single lga package includes st switching controller, power fets, inductor and all the support components. SPDC12L00010 operates over a wide input voltage range of 1.8 v to 14 v, supporting an output range of 0.6 v to 5 v. high level of integration and synchronous rectification allows the SPDC12L00010 to deliver up to 10 a continuous current at up to 93% efficiency, without external heat sink or airflow. the device is a complete stand alone surface mount power supply, that can be handled and assembled like a standard integrated circuit. moreover its low profile design permits the SPDC12L00010 to be soldered onto the back side of a printed circuit board, freeing up valuable board space. SPDC12L00010 is self protected against over voltage and short circuit conditions. a built in adjustable soft-start and inhibit guarantee correct functionality whatever the load is. pre-bias start up capability is in place as well power good output with programmable delay to avoid false signals. the device is packaged in a thermally enhanced, compact (15 x 15 mm) and low profile (3 mm) over molded land grid array (lga) package, suitable for automated assembly by standard surface mount equipment. the SPDC12L00010 is pb-free and rohs compliant.
SPDC12L00010 pin settings 5/24 2 pin settings 2.1 pin connection and mechan ical data (dimensions in mm) figure 1. pin connection 2.2 pin description am00542v1 table 2. pin description name function description j11 vaux auxiliary voltage. internally regulated 5 v voltage. it is us ed to supply the internal drivers and the voltage reference. k11 os oscillator set. connecting a resistor from this pin to sgnd or to vaux, the switching frequency can be increased or decreased. in ovp status the pin is pulled to 4.5 v (latched mode only). l2 vsense voltage sense. using this pin it is possible to recover the voltage drop on vout track. l3 vcc vcc. controller voltage supply pin. the oper ative voltage range for the internal controller is 4.5 v to 14 v
pin settings SPDC12L00010 6/24 name function description l4 pg power good. this pin is an open collector output, with a 10 k pull-up resistor connected to vaux. it is pulled low if the output volt age is not within specified thresholds (90%-110%). l5 pgdly power good delay. a capacitor connected between this pin and sgnd, introduce a delay between the internal pg comparator and the external signal rising edge. no delay can be introduced on the falling edge of pg signal. l6 sync synchronization. this is the master/slave pin. two or more devices can be synchronized connecting the sync pins together. l7 prg program. this pin allows following settings: - enable/disable the current sink mode capability after soft-start; - enable/disable the ovp latch mode; - setting uvlo threshold for 5 v or 12 v bus. l8 sgnd signal ground. all references are referred to these pins, internally connected to pgnd. l9 fb feed-back. this pin is connected to the error amplifier inverting input. l10 comp compensation. this pin is connected to the error amplifier output. l11 ss_inl soft-start_inhibit low the soft-start time is programmed connecting an external capacitor from this pin to sgnd; this pin can be used to inhibit the module. bank 1 vin dc input voltage. see section 5.18 on page 18 for mandatory condition. bank 2 pgnd return for input/output voltage source. bank 3 vout regulated power output. see section 5.19 on page 18 for mandatory condition. bank 4 ph phase this pins area is foreseen for module power losses dissipation; see section 5.20 on page 19 for details. table 2. pin description (continued)
SPDC12L00010 maximum ratings 7/24 3 maximum ratings 3.1 absolute maximum ratings 3.2 thermal data table 3. absolute maximum ratings symbol parameter value unit v k11 os to sgnd and pgnd -0.3 to 6 v v l2 vsense to sgnd and pgnd -0.3 to 18 v v l3 vcc to sgnd and pgnd -0.3 to 18 v v l4 pg to sgnd and pg nd -0.3 to 18 v v l5 pgdly to sgnd and pgnd -0.3 to 6 v v l6 sync to sgnd and pgnd -0.3 to 6 v v l7 prg to sgnd and pgnd -0.3 to 6 v v l9 fb to sgnd and pgnd -0.3 to 6 v v l10 comp to sgng and pgnd -0.3 to 6 v v l11 ss_inl to sgnd a nd pgnd -0.3 to 6 v v i vin to sgnd and pgnd -0.3 to 18 v v o vout to sgnd and pgnd -0.3 to 18 v i o maximum output current int. limited a table 4. table 3. thermal data symbol parameter value unit t stg storage temperature range -40 105 c t op operating temperature range -40 85 c
maximum ratings SPDC12L00010 8/24 3.3 thermal de-rating the thermal de-rating is obtained reducing the maximum output current, to limit the module temperature to the maximum allowable value. since a lot of parameters affect the module power dissipation, the best way to get a precise thermal de-rating is to measure the module temperature in the final application condition. for this purpose, the case top side must be monitored at the central point t1 (see figure 2 ); the maximum temperature allowable value at t1 is 125 c. figure 2. measurement points for thermal de-rating (top side) all data reported in the following tables are valid for free air condition and module placed on 25 cm 2 , 4 layers, 1.6 mm fr4 printed circuit board. table 5. thermal de-rating for vout = 5.0 v symbol parameter test condition value unit i o output current v in = 8 v t a = 75 c tbd a v in = 8 v t a = 80 c tbd v in = 8 v t a = 85 c tbd i o output current v in = 10 v t a = 70 c tbd a v in = 10 v t a = 75 c tbd v in = 10 v t a = 80 c tbd v in = 10 v t a = 85 c tbd i o output current v in = 12 v t a = 60 c tbd a v in = 12 v t a = 65 c tbd v in = 12 v t a = 70 c tbd v in = 12 v t a = 75 c tbd v in = 12 v t a = 80 c tbd v in = 12 v t a = 85 c tbd am00543v1
SPDC12L00010 maximum ratings 9/24 symbol parameter test condition value unit i o output current v in = 14 v t a = 50 c tbd a v in = 14 v t a = 55 c tbd v in = 14 v t a = 60 c tbd v in = 14 v t a = 65 c tbd v in = 14 v t a = 70 c tbd v in = 14 v t a = 75 c tbd v in = 14 v t a = 80 c tbd v in = 14 v t a = 85 c tbd table 6. thermal de-rating for vout = 3.3 v symbol parameter test condition value unit i o output current v in = 8 v t a = 80 c tbd a v in = 8 v t a = 85 c tbd i o output current v in = 10 v t a = 75 c tbd a v in = 10 v t a = 80 c tbd v in = 10 v t a = 85 c tbd i o output current v in = 12 v t a = 70 c tbd a v in = 12 v t a = 75 c tbd v in = 12 v t a = 80 c tbd v in = 12 v t a = 85 c tbd i o output current v in = 14 v t a = 65 c tbd a v in = 14 v t a = 70 c tbd v in = 14 v t a = 75 c tbd v in = 14 v t a = 80 c tbd v in = 14 v t a = 85 c tbd table 5. thermal de-rating for vout = 5.0 v (continued)
maximum ratings SPDC12L00010 10/24 table 7. thermal de-rating for vout = 2.5 v symbol parameter test condition value unit i o output current v in = 10 v t a = 80 c tbd a v in = 10 v t a = 85 c tbd i o output current v in = 12 v t a = 75 c tbd a v in = 12 v t a = 80 c tbd v in = 12 v t a = 85 c tbd i o output current v in = 14 v t a = 70 c tbd a v in = 14 v t a = 75 c tbd v in = 14 v t a = 80 c tbd v in = 14 v t a = 85 c tbd table 8. thermal de-rating for vout = 1.8 v symbol parameter test condition value unit i o output current v in = 10 v t a = 80 c tbd a v in = 10 v t a = 85 c tbd i o output current v in = 12 v t a = 80 c tbd a v in = 12 v t a = 85 c tbd i o output current v in = 14 v t a = 80 c tbd a v in = 14 v t a = 85 c tbd table 9. thermal de-rating for vout = 1.2 v symbol parameter test condition value unit i o output current v in = 14 v t a = 80 c tbd a v in = 14 v t a = 85 c tbd
SPDC12L00010 electrical characteristics 11/24 4 electrical characteristics table 10. electrical characteristics symbol parameter test condition min typ max unit v r ripple voltage v in = 12 v, i o = 10 a, c o = 2x330 f bw = 20 mhz 40 mvpp i o output current v in = 1.8 14 v 0 10 a i ol current limit v in = 1.8 14 v 12 a i q total quiescent current v cc = 12 v, i o = 0 a 65 ma i qst-by total stand-by quiescent current v ss_inl < 0.5 v 5 ma i ccq v cc quiescent current v cc = 12 v, i o = 0 a, os = open, v ss_inl > 0.5 v 35 ma i ccqst-by v cc stand-by quiescent current v cc = 12 v, i o = 0 a, os = open, v ss_inl < 0.5 v 5ma f s switching frequency v cc = 12 v, i o = 10 a, t a = 0 85 c 678 729 780 khz v fb feedback voltage (reference voltage) t a = -40 85 c 0.593 0.6 0.605 v v aux auxiliary voltage v cc = 5.5 14 v, i aux = 1 100 ma 4.5 5 5.5 v v ss_inl inhibit threshold device off 0.5 v i ss_inl soft-start current v ss_inl = 2 v 7 10 13 a v ss_inl = 0 0.5 v 20 30 45 v pg power good voltage low i pg = -5 ma 0.5 v v pghth power good high threshold (v fb /0.6) v fb rising 108 110 112 % v pglth power good low threshold (v fb /0.6) v fb falling 88 90 92 % v ovhth overvoltage high threshold (v fb /0.6) v fb rising 120 % v ovlth overvoltage low threshold (v fb /0.6) v fb falling 117 % v cconth v cc turn-on threshold 5 v bus, v in > 1.7 v 4.0 4.2 4.4 v 12 v bus, v in > 1.7 v 8.3 8.6 8.9 v ccoffth v cc turn-off threshold 5 v bus, v in > 1.7 v 3.6 3.8 4.0 v 12 v bus, v in > 1.7 v 7.4 7.7 8.0 v inhth v in high threshold v in rising 1.1 1.25 1.47 v v inlth v in low threshold v in falling 0.9 1.05 1.27 v
application information SPDC12L00010 12/24 5 application information 5.1 input voltage there are two voltage supply pins: vcc (pin l3), for cont roller voltage supply; vin (bank 1), for power circuit voltage supply. vcc and vin can be connected and supplied together; if vin is lower than 4.5 v, vc c must be supplied separately. the recommended maximum operating dc input voltage is 14 v. 5.2 auxiliary voltage vaux (pin j11) pin must be used to supply prg and os setting resistors. no capacitor is required. 5.3 inhibit function ss_inl (pin l11) allows putting the device in stand-by mode. with ss_inl lower than 0.5 v, the device is disabled and the current consumption is reduced to 5 ma, for vin = 12 v. with ss_inl higher than 0.5 v the device is enabled. since ss_inl has soft-start function, it is mandatory to implement the inhibit function using an open collector device (i.e. small signal transistor), to not influence the module behavior (see figure 3 ). figure 3. inhibit function am00544v1
SPDC12L00010 application information 13/24 5.4 soft-start the soft-start phase begins when both vcc and vin raise above their turn-on thresholds, otherwise the ss_inl pin is internally shorted to sgnd. a ramp is generated at ss_inl pin during start-up, charging the external capacitor css with an internal current generator. the initial value for this current is 30 a and it charges the capacitor up to 0.5 v, after that, it is reduced to 10 a until the final charge value approximately 4 v. in the meanwhile, the controller internal voltage reference raises to its final value, following the ss_inl pin voltage slope. during soft-start, the module provides a constant current protection, limiting the output current at the maximum value, without entering in hiccup mode. if there is not current limitation, the output voltage slope follows the ss_inl pin slope. the output voltage rise time, can be set choosing proper css value. the soft-start phase ends when the ss_inl pin voltage reaches 3.5 v. a capacitor css = 3 3 nf is present on the module, to perform a minimum soft-start time, suitable for co = 10000 f max. output capacitor; in this condition and with 10 a output current resistor load, the output voltage rise time is around 5ms, but the complete soft-start time is around 10ms. using the minimum output capacitor co = 660 f and with 10 a resistor load, the output voltage rise time is around 2 ms. 5.5 multiple units synchronization using more than one unit on the same circuit, it is possible to synchronize the switching frequency oscillators, connecti ng all sync (pin l6) together. the device with the higher s witching frequency will be the ma ster, while the other will be the slaves. the best way to synchronize two or more device s is to set same switching frequency, in any case, the switching frequencies can differ for a maximum of 50% of the lowest one. using and external clock signal, to synchroniz e one or more devices working at a different switching frequency, it is recommended to follow the below formula: f sw f ext 1.3f sw the phase shift between master and slaves is approximately 180.
application information SPDC12L00010 14/24 5.6 power good signal and power good delay the output voltage is monitored by fb (pin l9), if it is not within 10% (typ.) of the programmed value, the pg (pin l4) output is forced low. the pg signal can be delayed by adding an external capacitor on pgdly (pin l5), the delay can be calculated with the following formula: pg delay = 0.5 x c pgdly (pf) [ s] 5.7 oscillator setting the switching frequency is interna lly fixed to 729 khz, this valu e can be slightly varied using an external resistor r os connected between os (pin k11) and sgnd (l8) or vaux (pin j11). since the os pin is maintained at fixed voltage (typ. 1.2), the frequency is increased/decreased proportionally to the current sunk/sourced from/into the pin. in particular, connecting r os to sgnd the frequency is increased according the following formula: f sw = 729 + (9.88x10 6 /r os ) [khz] connecting r os to vaux the frequency is reduced according to the following formula: f sw = 729 - (30.1x10 6 /r os ) [khz] 5.8 current sink-mode connecting a proper resistor (see par. section 5.10 on page 15 ) from prg (pin l7) to vaux (pin j11), it is possible to select the sink-mode operation, that means to allow the output current to reverse its polarity into the converter output inductor. if the sink-mode is enabled, the converter can sink current from the load after soft-start; if the sink-mode is disabled, the converter never sinks current. note: when output low current operation is required (iout < 2 a), sink-mode operation is recommended, this condition improves output voltage transient response and reduces output voltage ripple.
SPDC12L00010 application information 15/24 5.9 under voltage lock out connecting a proper resistor (see par. section 5.10 ) from prg (pin l7) to vaux (pin j11), it is possible to select two different thresholds for uvlo: 4.2 v/3.8 v for 5 v input range; 8.6 v/7.7 v for 12 v input range. 5.10 program setting connecting a resistor from prg (pin l7) to vaux (pin j11), it is possible to select different operation modes, according to the following table: 5.11 voltage sensing using vsense (pin l2) it is possible to re cover the voltage drop on vout pcb track. connect vsense in a point closed to the load (see figure 4 ). using vsense connection, it will not recover the voltag e drop on pgnd pcb track. leaving vsense floating, the output volt age will be sensed at vout (bank 3). figure 4. voltage sensing table 11. program setting r prg uvlo. ovp sink-mode n.c. 5 v range not latched not 11 k ? not latched yes 6.2 k ? latched not 4.3 k ? latched yes 2.7 k ? 12 v range not latched not 1.8 k ? not latched yes 1.2 k ? latched not 0 ? latched yes
application information SPDC12L00010 16/24 5.12 output voltage programming adding a resistor rx between fb (pin l9) and sgnd (l8) or between fb and vsense (pin l2), it is possible to change the output voltage. connecting the resistor to sgnd the output voltage increase (see figure 5 a); connecting the resistor to vsense th e output voltage decrease (see figure 5 b). calculate the resistor for increasing output voltage with the following formula: r x = 0.6 / (v out ? 1.2) [k ] valid for v out > 1.2 v calculate the resistor for decreasing output voltage with the following formula: r x = (v out ? 0.6) / (1.2 ? v out ) [k ] valid for 0.6 < v out < 1.2 v the module output voltage is 1.2 v with r x = n.c. figure 5. output voltage programming 5.13 additional loop compensation if required by particular load condition, it is possible to change the feedback loop compensation, adding a pole with an external r-c network between fb (pin l9) and comp (pin l10) (see figure 6 a), or adding a zero with an external r-c network between fb and vsense (pin l2) (see figure 6 b). figure 6. additional loop compensation
SPDC12L00010 application information 17/24 5.14 output over voltage protection the device provides ovp: when the voltage sensed on fb (pin l9) reaches a value greater than 20% of reference, the on module low side driver is turned on and the converter stop switching operation. if the ovp not latched mode has been set, the on module low side mosfet is kept on, as long as the over voltage condition is detected. if ovp latched mode has been set, the low side mosfet is turned on and the os (pin k11) is forced high (4.5 v typ.), until vcc is toggled. it must be taken in account that there is an el ectrical network between the output terminal and fb, therefore the voltage at this pin is not a perfect replica of output voltage. if the converter is set to sink current, the low side mosfet could be turned on before the output voltage exceeds the over voltage threshold (109% typ.), because the error amplifier will change its balance in advance. if the sink-mode is disabled, the low side mosfet will be turned on only when the ovp operate, in this case a delay between the output voltage rising and the fb rising can appear and the ovp can operate late (126% typ.). 5.15 current limitation the device realizes the over current protection sensing the current on board high side mosfet and on board low side mosfet, therefore two current limits are set: peak current limit and valley current limit. the peak current protection is active when th e high side mosfet is turned on, the valley current protection is enabled when the low side mosfet is turned on. after soft-start is completed, if an over current occurs, the device enters in hiccup mode: both high side and low mosfets are turned off; the soft-start capacitor is discharged with a 10 a constant current; when the voltage on ss_inl (pin l11) reaches 0.5 v the soft-start phase restart. during the soft-start phase the ocp provides a constant current protection. 5.16 thermal shutdown when the controller junction temperature re aches 150 10 c, the device shutdown. both mosfet are turned off and the soft-start capacitor is discharged. the device does not restart until the junction temperature goes down to 120 c and until the voltage on the soft-start capacitor reaches 0.5 v.
application information SPDC12L00010 18/24 5.17 signal ground and power ground sgnd (l8) and pgnd (bank 2) are connected together on the module. connect to sgnd the capacitor for pgdly and ss_inl, the resistor for fb and os. connect to pgnd the return for ss_inl. it is important to not create a ground loop between sgnd, pgnd and other gnd present on the application circuit (see figure 7 ). figure 7. signal ground and power ground 5.18 input capacitors the input capacitor present on the module is not able to sustain the input rms current. connect 2 x 2.2 f 16 v x7r ceramic capacitor (cin) closed to the input pins vin and pgnd (bank 1 and bank 2), to satisfy minimum functional requirement. connect proper low impedance capacitors to reduce the input ripple current, according to the application requirement. 5.19 output capacitors the output capacitors present on the module are able to sustain output rms current. connect 2 x 330 f poscap sanyo capacitor (co) or equivalent, closed to the output pins vout and pgnd (bank 3 and ba nk 2), to guarantee output voltage stability and specified voltage ripple.
SPDC12L00010 application information 19/24 5.20 phase connection on the module bottom, there is an area relative to ph (bank 4) connection: this area is internally connected to the high side mosfet source and to the low side mosfet drain; this electrical point is used to dissi pate heat generated by the two mosfets. connect ph (bank 4), to an insulated copper area on the mother board, to ensure proper heat sink. since the ph signal contains very fast voltage transients, it is recommended to take in account possible inducted noise on mother board, i.e.: it is advised against to lead under the module printed circuit board tracks with susceptible signals.
package mechanical data SPDC12L00010 20/24 6 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com figure 8. package mechanical data am00542v1
SPDC12L00010 package mechanical data 21/24 6.1 soldering soldering phase has to be execute with care: in order to avoid undesired melting phenomenon, particular attention has to be take on the set up of the peak temperature. here following some suggestions for the temperature profile based on ipc/jedec j-std-020c, july 2004 recommendations. figure 9. soldering table 12. soldering profile feature pb free assembly average ramp up rate (t smax to t p ) 3 c / sec max preheat temperature min (t s min) temperature max (t s max) time (t s min to t s max) (t s ) 150 c 200 c 60 ? 100 sec time maintained above: temperature t l time t l 217 c 40 ? 70 sec peak temperature (t p ) 240 + 0 c time within 5 c of actual peak temperature (t p ) 10 ? 20 sec ramp down rate 6 c / sec time from 25 c to peak temperature 8 minutes max
package mechanical data SPDC12L00010 22/24 6.2 pcb footprint use figure 10 as suggested pcb footprint. figure 10. pcb footprint for SPDC12L00010 (dimensions in mm)
SPDC12L00010 revision history 23/24 7 revision history table 13. document revision history date revision changes 17-oct-2008 1 first release
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